library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity codeConverter1_tb is
end;

architecture bench of codeConverter1_tb is
   -- define the component
   component codeConverter1
      port( SW    :     IN    std_logic_vector  (  1  downto   0  );
            hex   :     OUT   std_logic_vector  (  6  downto   0  ) );
   end component;
   
   -- define the signals
   signal SW      :           std_logic_vector  (  1  downto   0  );
   signal hex     :           std_logic_vector  (  6  downto   0  );
   
   -- define a constant time period
   constant PERIOD : time := 5 ns;
   
begin
   -- component instantiation
   DUT   :  codeConverter1 port map (  SW => SW,
                                       hex => hex );
                                       
   test : process
   begin
      SW <= "00";
      wait for PERIOD;
      SW <= "01";
      wait for PERIOD;
      SW <= "10";
      wait for PERIOD;
      SW <= "11";
      wait for PERIOD;
      
      wait;
      
   end process;
end bench;


